T6C63 2001-12-04 1 toshiba cmos digital integrated circuit silicon monolithic T6C63 column driver for a dot matrix lcd the T6C63 is a 240-channel-output column driver for an stn dot matrix lcd. the T6C63 features a 42-v lcd drive voltage and a 20-mhz maximum operating frequency. the T6C63 is able to drive lcd panels with a duty ratio of up to 1 / 480. it is recommended for use with the t6c14. features display duty application : to 1/480 lcd drive signal : 240 data transfer : 8-bit bidirectional operating frequency : 20 mhz (v dd = 4.5 v) 12.5 mhz (v dd = 2.7 v) lcd drive voltage : 14 to 42 v (max 45 v) power supply voltage : 2.7 to 5.5 v operating temperature : ? 20 to 75c lcd drive output resistance: 700 ? (typ.), 1200 ? (max) (20 v, 1 / 13 bias) display-off function : when / dspof is l, all lcd drive outputs (o1 to o240) remain at the v 5 level. low power consumption : cascade connection and auto enable transfer functions are available. please contact toshiba or an authorized toshiba dealer for information on package dimensions. tcp (tape carrier package) lead pitch in out T6C63 (uan, 3n5) 0.60 0.074 unit: mm
T6C63 2001-12-04 2 block diagram
T6C63 2001-12-04 3 pin assignment the above diagram shows the pin configuration of the lsi chip, not that of the tape carrier package.
T6C63 2001-12-04 4 pin functions pin name i / o functions level o1 to o240 output output for lcd drive signal v 0 to v 5 eio1, eio2 i / o input / output for enable signal dir selects in or out. connect eio (in) of 1st lsi to l. for a cascade connection, connect eio (out) to eio (in) of next lsi when dir is high level, refer to as below. scp rising edge that input after falling edge of eio1(in) is set to be enable. at scp 20th clock, all 160-bit data latched. when eio2 (out) is disenable, it is always set to high level. in scp rising edge to next scp rising edge after 20th clock from chip enable, it is set to low level. di1 to di8 input input for data signal dir input (direction) input for data flow direction select / dspof input (display off) / dspof = l: display-off mode, (o1 to o240) remain at the v 5 level / dspof = h: display-on mode, (o1 to o240) are operational. lp input (latch pulse) display data is latched on falling edges of lp. when eio (in) = l, scplp = h enables the 1st lsi. when eio (in) is fixed to low level, 1st lsi in cascade connection is latched chip enable at /scp lp = high level. fr input (frame) input for frame signal scp input (shift clock pulse) input for shift clock pulse test D (test) fix to l or open v dd to v ss v dd D power supply for internal logic (5.0 v) v ss log D power supply for internal logic (0 v) v ss lr D power supply for lcd drive circuit v 5 lr D power supply for lcd drive circuit v 3 / 4 lr D power supply for lcd drive circuit v 2 / 1 lr D power supply for lcd drive circuit v 0 lr D power supply for lcd drive circuit v cc lr D power supply for lcd drive circuit D
T6C63 2001-12-04 5 relation between fr, data input and output level f r data input (di1 to di8) / dspof output level h l h v 2 h h h v 0 l l h v 3 l h h v 5 D D l v 5 data input format enable pin input data line and output buffers dir (eio1) (eio2) ( * 1) di1 di2 di3 di4 di5 di6 di7 di8 l o240 o239 o238 o237 o236 o235 o234 o233 h in out f o8 o7 o6 o5 o4 o3 o2 o1 l o1 o2 o3 o4 o5 o6 o7 o8 l out in f o233 o234 o235 o236 o237 o238 o239 o240 *1 : l: last data f: first data
T6C63 2001-12-04 6 T6C63-6 timing diagram
T6C63 2001-12-04 7 absolute maximum ratings (ensure that the following conditions are maintained: v cc v 0 v 2 v 3 v 5 v ss ) item symbol pin name rating unit supply voltage 1 v dd v dd ? 0.3 to 6.5 supply voltage 2 v cc v cc l / r ? 0.3 to 45.0 supply voltage 3 v 0 , v 2 v 0 l / r, v 2, 1 l / r ? 0.3 to v cc + 0.3 supply voltage 4 v 3 , v 5 v 3, 4 l / r, v 5 l / r ? 0.3 to v cc + 0.3 input voltage v in ( * 2) ? 0.3 to v dd + 0.3 v operating temperature t opr D ? 20 to 75 storage temperature t stg D ? 40 to 125 c *2 : scp, fr, lp, dir, eio1, eio2, di1 to di8, / dspof, test electrical characteristics dc characteristics (unless otherwise noted, v ss = 0v, v dd = 2.7 to 5.5 v, ta = ? 20 to 75c) item symbol test cir- cuit test condition min typ. max unit pin name supply voltage 1 v dd D D 2.7 5.0 5.5 v dd supply voltage 2 v cc D D 14.0 D 42.0 v cc l / r h level v ih D D 0.8 v dd D v dd input voltage l level v il D D 0 D 0.2 v dd scp, fr, lp, dir, eio1, eio2, di1 to di8, / dspof, test h level v oh D i oh = ? 0.5 ma v dd ? 0.5 D vdd output voltage l level v ol D i ol = 0.5 ma 0 D 0.5 v eio1 eio2 h level r oh D v out = v 0 ? 0.5 v (*3) D 700 1200 r om D v out = v 2 0.5 v (*3) D 700 1200 m level r om D v out = v 3 0.5 v (*3) D 700 1200 output resistance l level r ol D v out = v 5 + 0.5 v (*3) D 700 1200 ? o1 to o240 v dd v cc condition input current i il D 5.0 42 standby ? 10 D 10 a v 0 l / r v 2 l / r v 3 l / r v 5 l / r 5.0 D D 5.0 i dd ope 2.7 function ( * 4) D D 2.5 5.0 D D 2.0 i dd st / by 2.7 20 function ( * 5) D D 1.0 ma v dd current consumption i cc leak D 5.0 42 standby ? 10 D 10 a v cc l / r *3 : v cc = 20 v, 1 / 13 bias *4 : f scp = 13 mhz, f lp = 54 khz, f fr = 13.5 khz, f eio = 650 khz data format: every bit inverted, while internal data receriver is operating *5 : f scp = 13 mhz, f lp = 54 khz, f fr = 13.5 khz data format: every bit inverted, internal data receriver is sleeping
T6C63 2001-12-04 8 ac electrical characteristics test conditions ( 1 ) (unless otherwise noted, v ss = 0 v, v dd = 4.5 to 5.5 v, v cc = 1 4 to 42 v, ta = ? 20 to 75c) item symbol test condition min typ. max unit clock cycle t c D 50 D D scp pulse width t cwh , t cwl D 10 D D data set-up time t dsu D 8 D D data hold time t dhd D 10 D D scp rise / fall time t r , t f D D D ( * 6) lp rise time t lrp D 11 D D lp fall time t lfp D 7 D D lp pulse width t lw D 7 D D scp-to-lp delay time (slp lp) t sl D 0 D D lp-to-scp delay time (lp scp) t ls D 7 D D eio in rise time t eifp D 20 D D eio in pulse width t eiw D 9 D D scp-to-eio delay time (scp eio) t se D 1 D D eio-out delay time t eod ( * 7) D D 20 output delay time 1 (lp out) t pd1 D D D 400 output delay time 2 (fr out) t pd2 D D D 400 output delay time variation ( * 8) D D 0 30 ns *6 : t r , t f (t c ? t cwh ? t cwl ) / 2 and t r , t f 50 ns *7 : c l = 10 pf *8 : variation between output pins in t pd1 and t pd2 .
T6C63 2001-12-04 9 test conditions (2) (unless otherwise noted, v ss = 0 v, v dd = 2.7 to 4.5 v, v cc = 1 4 to 42 v, ta = ? 20 to 75c) item symbol test condition min typ. max unit clock cycle t c D 80 D D scp pulse width t cwh , t cwl D 20 D D data set-up time t dsu D 15 D D data hold time t dhd D 10 D D scp rise / fall time t r , t f D D ( * 9) lp rise time t lrp D 15 D D lp fall time t lfp D 14 D D lp pulse width t lw D 14 D D scp-to-lp delay time t sl D 2 D D lp-to-scp delay time t ls D 14 D D eio in fall time t eifp D 20 D D eio in pulse width t eiw D 14 D D scp-to-eio delay time t se D 2 D D eio-out delay time t eod ( * 10) D D 36 output delay time 1 (lp out) t pd1 D D D 500 output delay time 2 (fr out) t pd2 D D D 500 output delay time variations ( * 11) D D 0 50 ns *9 : t r , t f (t c ? t cwh ? t cwl ) / 2 and t r , t f 50 ns *10 : c l = 10 pf *11 : variation between output pins in t pd1 and t pd2 note: insert the bypass capacitor (0.1f) between v dd and v ss , and between v cc and v ss to decrease power supply noise. place the bypass capacitor as close to the lsi as possible.
T6C63 2001-12-04 10 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. polyimide base film is hard and thin. be careful not to injure yourself on the film or to scratch any other parts with the film. try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. when cutting out the film, try to ensure that the film shavings do not cause accidents. after use, treat the leftover film and reel spacers as industrial waste. light striking a semiconductor device generates electromotive force due to photoelectric effects. in some cases this can cause the device to malfunction. this is especially true for devices in which the surface (back), or side of the chip is exposed. when designing circuits, make sure that devices are protected against incident light from external sources. exposure to light both during regular operation and during inspection must be taken into account. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707ebe restrictions on product use
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